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10A ? Highly ? Integrated ? SupIRBuck TM ?
IR3475 ?
GATE ? DRIVE ? LOGIC ?
The ? gate ? drive ? logic ? features ? adaptive ? dead ? time, ??
diode ? emulation, ? and ? a ? minimum ? lower ? gate ? interval. ??
An ? adaptive ? dead ? time ? prevents ? the ? simultaneous ?
conduction ? of ? the ? upper ? and ? lower ? MOSFETs. ? The ? lower ?
gate ? voltage ? must ? be ? below ? approximately ? 1V ? after ? PWM ?
goes ? HIGH ? before ? the ? upper ? MOSFET ? can ? be ? gated ? on. ?
Also, ? the ? differential ? voltage ? between ? the ? upper ? gate ? and ?
PHASE ? must ? be ? below ? approximately ? 1V ? after ? PWM ? goes ?
LOW ? before ? the ? lower ? MOSFET ? can ? be ? gated ? on. ?
The ? upper ? MOSFET ? is ? gated ? on ? after ? the ? adaptive ? delay ??
capacitor, ? the ? magnitude ? of ? the ? AC ? voltage ? ripple ? is ?
determined ? by ? the ? total ? inductor ? ripple ? current ? flowing ?
through ? the ? total ? equivalent ? series ? resistance ? (ESR) ? of ? the ?
output ? capacitor ? bank. ? ?
One ? can ? use ? equation ? 5 ? to ? find ? the ? required ? inductance. ??
Δ I ? is ? defined ? as ? shown ? in ? Figure ? 27. ? The ? main ? advantage ??
of ? small ? inductance ? is ? increased ? inductor ? current ? slew ? rate ?
during ? a ? load ? transient, ? which ? leads ? to ? a ? smaller ? output ?
capacitance ? requirement ? as ? discussed ? in ? the ? Output ?
Capacitor ? Selection ? section. ? The ? drawback ? of ? using ? smaller ?
inductances ? is ? increased ? switching ? power ? loss ? in ? the ? upper ?
MOSFET, ? which ? reduces ? the ? system ? efficiency ? and ?
increases ? the ? thermal ? dissipation. ?
for ? PWM ? = ? HIGH ? and ? the ? lower ? MOSFET ? is ? gated ? on ? after ?
the ? adaptive ? delay ? for ? PWM ? = ? LOW. ? When ? FCCM ? = ? LOW, ?
the ? lower ? MOSFET ? is ? driven ? ‘off’ ? when ? the ? ZCROSS ? signal ?
?
Δ I =
T ON ? ( V IN ? V OUT )
2 ? L
(5)
indicates ? that ? the ? inductor ? current ? is ? about ? to ? reverse ?
direction. ? The ? ZCROSS ? comparator ? monitors ? the ? PHASE ?
voltage ? to ? determine ? when ? to ? turn ? off ? the ? lower ? MOSFET. ?
The ? lower ? MOSFET ? stays ? ‘off’ ? until ? the ? next ? PWM ? falling ?
edge. ? When ? the ? lower ? peak ? of ? the ? inductor ? current ? is ?
above ? zero, ? IR3475 ? operates ? in ? continuous ? conduction ?
mode. ? The ? continuous ? conduction ? mode ? can ? also ? be ?
selected ? for ? all ? load ? current ? levels ? by ? pulling ? FCCM ? to ?
1
? f 2 ( t ) ? dt
Ts ∫ 0
I IN_RMS =
1 ? Δ I ?
HIGH. ?
Whenever ? the ? upper ? MOSFET ? is ? turned ? ‘off’, ? it ? stays ??
‘off’ ? for ? the ? Min ? Off ? Time ? denoted ? in ? the ? Electrical ?
Specifications . ? This ? minimum ? duration ? allows ? time ? to ?
recharge ? the ? bootstrap ? capacitor ? and ? allows ? the ? over ?
current ? monitor ? to ? sample ? the ? PHASE ? voltage. ?
?
COMPONENT ? SELECTION ?
?
Selection ? of ? components ? for ? the ? converter ? is ? an ? iterative ?
process ? which ? involves ? meeting ? the ? specifications ? and ?
tradeoffs ? between ? performance ? and ? cost. ? The ? following ?
sections ? will ? guide ? one ? through ? the ? process. ?
Inductor ? Selection ??
Inductor ? selection ? involves ? meeting ? the ? steady ? state ?
output ? ripple ? requirement, ? minimizing ? the ? switching ? loss ??
of ? the ? upper ? MOSFET, ? meeting ? transient ? response ?
specifications ? and ? minimizing ? the ? output ? capacitance. ??
The ? output ? voltage ? includes ? a ? DC ? voltage ? and ? a ? small ? AC ?
ripple ? component ? due ? to ? the ? low ? pass ? filter ? which ? has ?
incomplete ? attenuation ? of ? the ? switching ? harmonics. ?
Neglecting ? the ? inductance ? in ? series ? with ? the ? output ?
Figure ? 27: ? Typical ? Input ? Current ? Waveform ?
Input ? Capacitor ? Selection ??
The ? main ? function ? of ? the ? input ? capacitor ? bank ? is ? to ? provide ?
the ? input ? ripple ? current ? and ? fast ? slew ? rate ? current ? during ?
the ? load ? current ? step ? up. ? The ? input ? capacitor ? bank ? must ?
have ? adequate ? ripple ? current ? carrying ? capability ? to ? handle ?
the ? total ? RMS ? current. ? Figure ? 27 ? shows ? a ? typical ? input ?
current. ? Equation ? 6 ? shows ? the ? RMS ? input ? current. ???
The ? RMS ? input ? current ? contains ? the ? DC ? load ? current ? and ?
the ? inductor ? ripple ? current. ? As ? shown ? in ? equation ? 5, ? the ?
inductor ? ripple ? current ? is ? unrelated ? to ? the ? load ? current. ?
The ? maximum ? RMS ? input ? current ? occurs ? at ? the ? maximum ?
output ? current. ?? The ? maximum ? power ? dissipation ? in ? the ?
input ? capacitor ? equals ? the ? square ? of ? the ? maximum ? RMS ?
input ? current ? times ? the ? input ? capacitor’s ? total ? ESR. ??
Ts
?
?
2
? = I OUT ? T ON ? Fs ? 1 + ? ? ? (6)
3 ? I OUT ?
The ? voltage ? rating ? of ? the ? input ? capacitor ? needs ? to ? be ?
greater ? than ? the ? maximum ? input ? voltage ? because ? of ? high ?
frequency ? ringing ? at ? the ? phase ? node. ? The ? typical ?
percentage ? is ? 25%. ?
14
March ? 27, ? 2013 ?? | ?? V2.2 ?? | ?? PD97602
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